This invention describes a method for exposing contacts on separate HFETS, HBTs, HEMTs prior to the final metallization step of an integrated circuit manufacture. The method improves the circuit yield by reducing the opportunity for the final interconnection of the circuit to short out the circuit or fail to make a connection at all.
FIGS. 1 a-e describes the prior art method of preparing built up integrated circuits for interconnection with metallization layers. The circuit 100 is first built of a number of layers. Next, portions of the exposed layers are cut away, doped and in some cases metallized to create the structure in FIG. 1a 
Integrated circuits as shown in FIG. 1a typically need active devices such as transistors and passive devices such as resistors. These may be built on the integrated circuit as shown in FIG. 1b. For example, to build a resistor in FIG. 1b a layer 32 of silicone nitride is added then a layer 30 of a thin film resistive material. The locations where a resistor are desired is covered in photo resist, a mask is used to control the exposure of the photo resist to light, then the unexposed photo resist is removed leaving the photo resist 34 over the desired resistor location. Next, in step 36 the layers 30 and 32 are etched away with carbon tetrafluoride or sulfur hexafluoride or other etchant depending on the composition of layers 32 and 30. Finally, the photo resist 34 is removed leaving the device 100 with a passive resistor 40 ready for interconnection.
The interconnection process begins with constructing contacts 50, 52 and 54 to the terminals of the device using techniques known in the art as shown in FIG. 1d. Note that the height of the contact above the terminals is 60 or D1 and the height of a terminal is 62 or D2. Next, in FIG. 1d, an Interlayer Dielectric (ILD) layer 64 is applied over the whole device. The ILD layer 64 may be a spun on glass, Benzene CycloButane, Polyimide, silicon oxide or silicon nitride or similar materials. The ILD layer 64 is etched back in step 66 in FIG. 1e to expose the contacts 50, 52 and 54. The etching of the ILD has to be enough to expose all contacts but not so much as to expose any terminals 10, 12 or 14. If the terminals are exposed and the metallization layers applied there is a chance the metallization will make undesired contact with the exposed terminals. Alternatively, if the etching is enough to expose some contacts but not all then the metallization process will end with some connections not made. Either event results in failed circuits that reduce the yield.
FIG. 2a illustrates how over etching the ILD 318 can lead to undesired circuit interconnections. In FIG. 2a, two groups of devices are built on the same integrated circuit, the denser devices are 240 and the more isolated device is 250. Devices 240 and 250 may be near each other or far apart where near and far are relative to the thickness of the ILD layer 318. Each device 240, 250 has a terminal 14 and a contact 50. The contacts are at a height 62. An ILD layer 318 is added over all devices. Those devices near each other are more likely to have the same thickness of ILD 318 over each device. The ILD layer 318 over an isolated device 250 will likely have a different thickness 220. Varying thicknesses may result from the topography, non uniform application of the coating or other influences.
The ILD layer 318 in FIG. 2a is etched back a thickness 210 (D2) to reveal the contacts 50. However, in the case of device 250 the etch back should be only the thickness 220 (D1). If the difference in thicknesses D2−D1 is greater than the height 62 of the contact 50 then the etch back process will reveal the terminal 14 on device 250. A subsequent metallization layer may make an undesired connection to terminal 14.
The equally undesired alternative of insufficient etch back is shown in FIG. 2b. In FIG. 2b the ILD 318 is etched back a thickness 220 (D2) to expose contact 50 of device 250. However, this is insufficient to expose contact 50 of devices 240. A subsequent metallization layer will fail to contact devices 240 leading to circuit failure and reduced yield.
Even if the etch back allows all necessary connections, the interconnection metallization process will create parasitic capacitance between the metallization layer and any contacts 50 not connected to the metallization layer. One way to reduce the parasitic capacitance is to increase the separation between the metallization layer and any underlying contacts 50
A solution is needed to desensitize the etch back of the ILD layer 318, prior to metallization, to variations in thickness of the ILD layer. It would be beneficial to reduce the parasitic capacitance too.
SUMMARY
In a first embodiment, applying a first layer which is usually an etch stop layer over the contacts and devices on an integrated circuit. Then etching away the first layer over the contacts of the devices of an integrated circuit. Then covering the devices and contacts of the integrated circuit with a second layer of a different material. Then etching away the second layer with an etchant that etches the second layer at a rate greater then twice the rate of the etchant etching the first layer.
In a second embodiment, the first embodiment where the first layer is an etch stop layer that may be made of silicon oxide, silicon nitride or polysilicone.
In another embodiment, the first embodiment where the second layer comprises an Interlayer Dielectric.
In a fourth embodiment, a method of preparing a semiconductor integrated circuit for interconnection comprising coating one or more devices of the integrated circuit with a non conductive first dielectric layer, then masking off none or more contacts of one or more devices. Next, etch away the first dielectric layer covering none or more contacts of one or more devices with a first etching material, then covering the one or more devices of the integrated circuit with a second dielectric layer. Next, planarize the second dielectric layer without exposing one or more contacts of one or more devices, then masking off none or more contacts of one or more devices. Next, etching away the second dielectric layer covering the one or more devices with a second etching material, wherein the second etching material removes the second dielectric layer at least at twice the rate the second etching material removes the first dielectric layer.
In a fifth embodiment, the method of the fourth embodiment wherein the first dielectric layer comprises silicon oxide, silicon nitride or polysilicone.
In a sixth embodiment, the method of the fourth embodiment wherein the second dielectric layer comprises silicon oxide, silicon nitride, polysilicone, polyimide, benzenecyclobutane, or spun on glass.
In another embodiment, the method of the fourth embodiment wherein the second etching material comprises a fluorine based compound.
In another embodiment, the previous embodiment wherein the fluorine based compound comprises carbon tetraflouride or sulfur hexafluoride.
In another embodiment, the method of the fourth embodiment wherein the semiconductor integrated circuit comprises one or more devices made of Group III-V or Group II-VI materials.